The document DE 101 57 361 discloses an electronic device comprising a stack of semiconductor chips, an intermediate carrier being arranged as spacer between the stacked semiconductor chips in order to ensure that the interspace between the stacked semiconductor chips is sufficient, so that bonding connections of a base chip are not damaged by the stacked semiconductor chip projecting beyond the base chip. The known electronic device involves stacking semiconductor chips which have a multiplicity of contact areas in their edge regions which are electrically connected to corresponding external contacts of the electronic device via the bonding connections. The spacer having an insulating effect is accordingly intended to ensure that a plastics composition having an insulating effect fills the interspace between the stacked semiconductor chips in such a way that the edges of the stacked semiconductor chip that project beyond the base chip are supported. One disadvantage of a spacer of this type is that it can only perform mechanical functions, and is unsuitable for the coupling and forwarding of currents and signals.
The document DE 196 35 582 C1 discloses a power semiconductor component for bridge circuits comprising so-called high-side switches or low-side switches, which has a first base power semiconductor chip containing a vertical first transistor, and a further, second power semiconductor chip having a second vertical transistor is mounted on the first base power semiconductor chip, so that the conduction paths of the two transistors are connected in series. An arrangement of this type can be extended in a simple manner to form a full bridge, as shown in FIGS. 6 and 7.
FIG. 6 shows the bridge circuit of power semiconductor chips known from the prior art, the base power semiconductor chip 1 being mounted on a so-called heat sink area 6 and containing two semiconductor switches H1, H2 insulated from one another on the source side. The two drain connections of the semiconductor switches H1 and H2 form the rear side of the base power semiconductor chip 1, said rear side being mounted on the heat sink area 6. Two further power semiconductor chips 2 and 3 are then stacked on the source areas of the two transistors H1 and H2, said source areas being situated on the top side of the base power semiconductor chip 1.
These stacked power semiconductor chips 2 and 3 respectively have further power transistors L1 and L2. In this respect, the drain regions of the transistors L1 and L2 are mounted on the respective source regions of the power transistors H1 and H2 and form the nodes 4 and 5, which can be connected via the respective external connections 10 and 14. The respective source regions of the power transistors L1 and L2 can likewise be contact-connected via the external connections 7 and 8 by bonding. The external connections 9, 11, 13 and 15 serve for driving the respective transistors H1, H2, L1 and L2 of the full bridge.
One realization of the bridge circuit 16 is shown in FIG. 7, in which the bridge circuit 16 is arranged in a surface-mountable housing 20 with external connections 22. In this case, the two source areas of the transistors H1 and H2 situated at the surface of the base power semiconductor chip 1 are larger than the second and third stacked power semiconductor chips 2 and 3 mounted on them. As a result, contact can be made by the contact-making areas at the nodes 4 and 5 in a simple manner by means of bonding wires 24 and 26 with the external connections 22. The source areas of the semiconductor chips 2 and 3 are also likewise connected to respective externally accessible connections 22 from above by means of bonding wires 23 and 25.
This arrangement has the disadvantage that the drain connection basic area of the low-side switches L1 and L2 contained in the power semiconductor chips 2 and 3 is smaller than the respective source contact-making areas of the high-side switches H1 and H2 in the base power semiconductor chip 1. This is associated with the disadvantage that the permissible current consumption of the bridge circuit branches is significantly restricted by the reduced size of the stacked power semiconductor components 2 and 3.